LATENCY 42ns -33% THROUGHPUT 1M+ evt/s CACHE_MISS -38% optimized P99 250ns stable CONCURRENT 1000 req/s COMPRESSION 48x ratio UPTIME 99.5% SLA SHARPE 2.1 ratio
LATENCY 42ns -33% THROUGHPUT 1M+ evt/s CACHE_MISS -38% optimized P99 250ns stable CONCURRENT 1000 req/s COMPRESSION 48x ratio UPTIME 99.5% SLA SHARPE 2.1 ratio
~/aayush $ ./portfolio --run

Hi, I'm

Aayush Parashar

|

Building microsecond-latency trading infrastructure and AI systems.
Specialized in C++, systems programming, and quantitative development.

C++17/20/23 Python TypeScript SIMD Lock-Free PyTorch
GitHub LinkedIn Email

About

I'm a Software Engineer based in Sydney, Australia, specializing in low-latency systems, quantitative development, and AI/ML infrastructure.

Currently pursuing a B.I.T at Torrens University (WAM 85 - High Distinction) with a 50% Merit Scholarship, graduating July 2027.

My work spans from building nanosecond-latency order matching engines to deploying real-time AI inference systems handling 1,000+ concurrent requests.

42ns p50 Matching Engine Latency
1K+ Concurrent Requests Handled
39th SIG Algothon 2025 Rank
501 All India Rank (150K+)

Technical Skills

Languages

C++17/20/23 C Python SQL TypeScript

Low-Latency Systems

Cache-Line Alignment Lock-Free Queues SIMD (AVX-512/NEON) NUMA-Aware Design Slab Allocators Memory Ordering

Profiling & Benchmarking

Linux perf DTrace FlameGraphs Google Benchmark CPU Pinning

Quantitative

Kalman Filtering Monte Carlo Stochastic Processes Time-Series Analysis Risk Metrics

Infrastructure

Linux Docker Redis PostgreSQL FastAPI CI/CD

AI/ML

INT8 Quantization ARM64 Deployment PyTorch TensorFlow Neo4j

Experience

AI Research Engineer

Signal Processing Lab, Torrens University

Jul 2025 - Present
  • Refactored inference pipelines to Structure-of-Arrays (SoA) layouts, reducing L2 cache misses by 38% and median latency by 33% (12us to 8us)
  • Deployed INT8-quantized models on ARM64 (NEON); optimized ECG signal compression achieving up to 48x ratio
  • Scaled real-time inference to 1,000 concurrent requests with p99 100ms; improved calibration (ECE 0.433 to 0.127)
  • Benchmarked deployment: 16.2ms (V100), 47ms (T4) for cost-performance analysis

Software Engineer (Founding Team)

Scinter (AI Startup)

Dec 2024 - Mar 2025
  • Architected analytics backend handling 10K+ daily queries; Redis caching + PostgreSQL optimization reduced p95 latency by 67% (600ms to 200ms)
  • Implemented blue-green CI/CD pipelines with Docker and automated rollback, maintaining 99.5% uptime
  • Designed async data ingestion layer using FastAPI + AsyncIO for high-throughput event processing

Projects

Limit Order Book & Matching Engine

C++17/20

FIFO matching engine with cache-line alignment, data-oriented design, and hot-path allocation elimination via slab memory pools.

42ns p50 latency
250ns p99 latency
O(1) top-of-book
View on GitHub

HFT Execution Simulator

C++23

Event-driven backtesting framework with deterministic microsecond-resolution replay and lock-free SPSC ring buffers.

1M+ events/sec
Zero contention
View on GitHub

Arena-Based Vector Library

C

Custom arena allocator and dynamic vector with bump-pointer allocation for zero-fragmentation memory management.

Zero fragmentation
RAII lifetime mgmt
View on GitHub

MEDICO - Medical Diagnostic System

Python

Multi-agent AI diagnostic pipeline using ensemble LLM reasoning with Neo4j knowledge graph for explainable inference.

88% accuracy
Neo4j knowledge graph
View on GitHub

Service Telemetry Monitor

Python / FastAPI

Real-time service health monitoring dashboard with async polling, Discord webhook alerting, and latency visualization.

Real-time monitoring
Async architecture
View on GitHub

Scinterweb Analytics Platform

TypeScript / React

Production analytics frontend with real-time charting, user session management, and responsive dashboards.

500+ beta users
React frontend
View on GitHub

Research & Publications

Under Review

ECG-ASQ-LLM: Adaptive Semantic Quantization

IEEE Transactions on Biomedical Engineering, 2025

Scaled to 1K concurrent requests; deployment latency: 16.2ms (V100), 47ms (T4)

Working Paper

QHeartAI: Physics-Inspired Mathematics for ECG Analysis

DOI available on request, 2025

Interpretable framework using unitary transforms and complex-valued representations for lead coupling invariants

In Preparation

Sleep-LLM: Automated Sleep Stage Classification

2025

End-to-end EEG pipeline for 5-class sleep staging using transformer-based modelling on Sleep-EDF dataset

Achievements

SIG Algothon 2025

Team Rank 39th / 240 (Top 16%)

Mean-reversion strategies using Kalman-filtered signals

Government of India Scholarship

$10,000 Meritorious Candidate

All India Rank 501

UPTU/AKTU Entrance Exam

Out of 150,000+ candidates

Mathematics Olympiad

5x School Champion

Uttar Pradesh State 3rd Place

Apple Foundation Program

Completed Sep 2024

Swift, app design, product thinking

50% Merit Scholarship

Torrens University Australia

WAM 85 (High Distinction)

Learning Streak

What I'm currently learning and building. Updated regularly.

0 Day Streak
Best 45 days

Activity This Year

Less
More

FPGA Development

Verilog/VHDL for ultra-low latency market data processing

35% Complete
In Progress

Rust for Systems Programming

Memory safety without garbage collection for trading systems

60% Complete
In Progress

Derivative Contracts

Options pricing, Greeks, and volatility modeling

20% Complete
Upcoming

Lock-Free Data Structures

SPSC/MPMC queues, atomic operations, memory ordering

Completed
Done

Want to suggest what I should learn next?

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Get In Touch

I'm currently open to opportunities in quantitative development, low-latency systems engineering, and AI/ML infrastructure roles.

Aayush.parashar@student.torrens.edu.au GitHub LinkedIn

Sydney, AU | +61 416 360 675